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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. SN65LBC175A-EP sllseu5 ? december 2016 SN65LBC175A-EP quadruple rs-485 differential line receiver 1 (1) the signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second). 1 features 1 ? designed for tia/eia-485, tia/eia-422 and iso 8482 applications ? signaling rates (1) exceeding 50 mbps ? fail-safe in bus short-circuit, open-circuit, and idle-bus conditions ? esd protection on bus inputs exceeds 6 kv ? common-mode bus input range ? 7 v to 12 v ? propagation delay times < 18 ns ? low standby power consumption < 32 a ? pin-compatible upgrade for mc3486, ds96f175, ltc489, and sn75175 2 applications ? supports defense, aerospace, and medical applications ? controlled baseline ? one assembly and test site ? one fabrication site ? extended product life cycle ? extended product-change notification ? product traceability 3 description the SN65LBC175A-EP is a quadruple differential line receiver with 3-state outputs, designed for tia/eia- 485 (rs-485), tia/eia-422 (rs-422), and iso 8482 (euro rs-485) applications. this device is optimized for balanced multipoint bus communication at data rates up to and exceeding 50 million bits per second. the transmission media may be twisted-pair cables, printed-circuit board traces, or backplanes. the ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. the receiver operates over a wide range of positive and negative common-mode input voltages, and features esd protection to 6 kv, making it suitable for high-speed multipoint data transmission applications in harsh environments. these devices are designed using linbicmos ? , facilitating low power consumption and robustness. two en inputs provide pair-wise enable control, or these can be tied together externally to enable all four drivers with the same signal. . device information (1) part number package body size (nom) SN65LBC175A-EP soic (16) 9.90 mm 3.90 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. logic diagram 1a1b 1y 2a2b 2y 3a3b 3y 4a4b 4y 1,2en 3,4en copyright ? 2016, texas instruments incorporated productfolder sample &buy technical documents tools & software support &community
2 SN65LBC175A-EP sllseu5 ? december 2016 www.ti.com product folder links: SN65LBC175A-EP submit documentation feedback copyright ? 2016, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings .............................................................. 4 6.3 recommended operating conditions ....................... 4 6.4 thermal information .................................................. 4 6.5 electrical characteristics ........................................... 5 6.6 switching characteristics .......................................... 5 6.7 typical characteristics .............................................. 7 7 parameter measurement information .................. 8 8 detailed description ............................................ 10 8.1 overview ................................................................. 10 8.2 functional block diagram ....................................... 10 8.3 feature description ................................................. 10 8.4 device functional modes ........................................ 10 9 application and implementation ........................ 12 9.1 application information ............................................ 12 9.2 typical application .................................................. 12 10 power supply recommendations ..................... 14 11 layout ................................................................... 14 11.1 layout guidelines ................................................. 14 11.2 layout example .................................................... 14 12 device and documentation support ................. 15 12.1 receiving notification of documentation updates 15 12.2 community resources .......................................... 15 12.3 trademarks ........................................................... 15 12.4 electrostatic discharge caution ............................ 15 12.5 glossary ................................................................ 15 13 mechanical, packaging, and orderable information ........................................................... 16 4 revision history date revision notes december 2016 * initial release.
3 SN65LBC175A-EP www.ti.com sllseu5 ? december 2016 product folder links: SN65LBC175A-EP submit documentation feedback copyright ? 2016, texas instruments incorporated 5 pin configuration and functions d package 16-pin soic top view pin functions pin i/o description name no. 1a 2 i rs-485 differential input (noninverting). 1b 1 i rs-485 differential input (inverting). 1y 3 o logic level output. 2a 6 i rs-485 differential input (noninverting). 2b 7 i rs-485 differential input (inverting). 2y 5 o logic level output. 3a 10 i rs-485 differential input (noninverting). 3b 9 i rs-485 differential input (inverting). 3y 11 o logic level output. 4a 14 i rs-485 differential input (noninverting). 4b 15 i rs-485 differential input (inverting). 4y 13 o logic level output. 1,2en 4 i active-low and active-high select. 3,4en 12 i active-low and active-high select. gnd 8 ? ground. v cc 16 ? power supply. 1 1b 16 vcc 2 1a 15 4b 3 1y 14 4a 4 1,2en 13 4y 5 2y 12 3,4en 6 2a 11 3y 7 2b 10 3a 8 gnd 9 3b not to scale
4 SN65LBC175A-EP sllseu5 ? december 2016 www.ti.com product folder links: SN65LBC175A-EP submit documentation feedback copyright ? 2016, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values, except differential i/o bus voltages, are with respect to gnd and are steady-state (unless otherwise specified). 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit supply voltage, v cc (2) ? 0.3 6 v voltage at any bus input (steady state), a and b ? 10 15 v voltage at any bus (transient pulse through 100 ? , see figure 10 ) ? 30 30 v input voltage at 1,2en and 3,4en, v i ? 0.5 v cc + 0.5 v receiver output current, i o ? 10 10 ma storage temperature, t stg ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) a and b to gnd 6000 v all pins 5000 charged-device model (cdm), per jedec specification jesd22-c101 (2) all pins 2000 6.3 recommended operating conditions min nom max unit v cc supply voltage 4.75 5 5.25 v voltage at any bus terminal a, b ? 7 12 v v ih high-level input voltage en 2 v cc v v il low-level input voltage 0 0.8 v output current y ? 8 8 ma t j junction temperature ? 55 125 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.4 thermal information thermal metric (1) SN65LBC175A-EP units d (soic) 16 pins ja junction-to-ambient thermal resistance 78 c/w jctop junction-to-case (top) thermal resistance 39.5 c/w jb junction-to-board thermal resistance 35.4 c/w jt junction-to-top characterization parameter 8.5 c/w jb junction-to-board characterization parameter 35.1 c/w
5 SN65LBC175A-EP www.ti.com sllseu5 ? december 2016 product folder links: SN65LBC175A-EP submit documentation feedback copyright ? 2016, texas instruments incorporated (1) all typical values are at v cc = 5 v and 25 c. 6.5 electrical characteristics over recommended operating conditions parameter test conditions min typ (1) max unit v it+ positive-going differential input voltage threshold ? 7 v v cm 12 v (v cm = (v a + v b ) / 2) ? 80 ? 10 mv v it- negative-going differential input voltage threshold ? 200 ? 120 mv v hys hysteresis voltage (v it+ ? v it ? ) ? 40 mv v ik input clamp voltage i i = ? 18 ma ? 1.5 ? 0.8 v v oh high-level output voltage v id = 200 mv, i oh = ? 8 ma see figure 6 2.7 4.8 v v ol low-level output voltage v id = ? 200 mv, i ol = 8 ma 0.2 0.4 v i oz high-impedance-state output current v o = 0 v to v cc ? 1 1 a i i line input current other input at 0 v, v cc = 0 v or 5 v v i = 12 v 0.9 ma v i = ? 7 v ? 0.7 i ih high-level input current enable inputs 110 a i il low-level input current ? 100 a r i input resistance a, b inputs 12 k i cc supply current v id = 5 v 1,2en, 3,4en at 0 v 32 a no load 1,2en, 3,4en at v cc 11 16 ma (1) output skew (t sk(o) ) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected together. (2) part-to-part skew (t sk(pp) ) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same input signals, the same supply voltages, at the same temperature, and have identical packages and test circuits. 6.6 switching characteristics over recommended operating conditions parameter test conditions min typ max unit t r output rise time v id = ? 3 v to 3 v, see figure 7 2 7 ns t f output fall time 2 7 ns t plh propagation delay time, low-to-high level output 8 12 18 ns t phl propagation delay time, high-to-low level output 8 12 18 ns t pzh propagation delay time, high-impedance to high-level output see figure 8 27 39 ns t phz propagation delay time, high-level-output to high-impedance 7 24 ns t pzl propagation delay time, high-impedance to low-level output see figure 9 29 39 ns t plz propagation delay time, low-level-output to high-impedance 12 18 ns t sk(p) pulse skew (|t plh ? t phl |) 0.2 2 ns t sk(o) output skew (1) 3 ns t sk(pp) part-to-part skew (2) 3 ns
6 SN65LBC175A-EP sllseu5 ? december 2016 www.ti.com product folder links: SN65LBC175A-EP submit documentation feedback copyright ? 2016, texas instruments incorporated (1) see data sheet for absolute maximum and minimum recommended operating conditions. (2) silicon operating life design goal is 10 years at 105 c junction temperature (does not include package interconnect life). (3) enhanced plastic product disclaimer applies. figure 1. SN65LBC175A-EP wirebond life derating chart operating junction temperature ( q c) life (yr) 85 105 125 145 165 0.1 1 10 100 d001
7 SN65LBC175A-EP www.ti.com sllseu5 ? december 2016 product folder links: SN65LBC175A-EP submit documentation feedback copyright ? 2016, texas instruments incorporated 6.7 typical characteristics figure 2. bus input current vs bus input voltage v cc = 5 v t a = 25 c figure 3. output voltage vs differential input voltage figure 4. supply current vs signaling rate (all four channels) figure 5. propagation delay time vs free-air temperature ?600 ?400 ?200 0 200 400 600 800 ?10 ?5 0 5 10 15 v cc = 0 v v cc = 5 v bus input current ? bus input voltage ? v a 0 1 2 3 4 5 6 ?150 ?100 ?50 0 50 v ic = ?7 v v ic = 0 v v ic = 12 v v ic = ?7 v v ic = 0 v v ic = 12 v ? output voltage ? v differential input voltage ? mv v o 0 10 20 30 40 50 60 1 10 100 v cc = 5 v, no load v cc = 4.75 v, c l = 15 pf v cc = 5 v, c l = 15 pf v cc = 5.25 v, c l = 15 pf ? supply current ? ma signaling rate (all four channels) ? mbps i cc operating junction temperature ( q c) propagation delay time (ns) -55 -35 -15 5 25 45 65 85 105 125 11 11.5 12 12.5 13 13.5 14 d005 tphl tplh
8 SN65LBC175A-EP sllseu5 ? december 2016 www.ti.com product folder links: SN65LBC175A-EP submit documentation feedback copyright ? 2016, texas instruments incorporated 7 parameter measurement information figure 6. voltage and current definitions figure 7. switching test circuit and waveforms figure 8. test circuit waveforms ? t pzh and t phz figure 9. test circuit waveforms ? t pzl and t plz ab generator 50 y 1.5 v 1.5 v 3 v0 v t pzl t plz v ol v cc en y v ol + 0.5 v 1.5 v ?1.5 v en 1 k v cc generators: prr = 1 mhz, 50% duty cycle, t r <6 ns, z o = 50 c l = 15 pf (includes probe and jig capacitance) ab generator 50 y c l = 15 pf 1.5 v 1.5 v 3 v0 v t pzh t phz v oh gnd v oh ?0.5 v 1.5 v 1.5 v 1 k v cc generators: prr = 1 mhz, 50% duty cycle, t r <6 ns, z o = 50 en c l = 15 pf (includes probe and jig capacitance) en y ab generator 50 generator 50 y c l = 15 pf (includes probe and jig capacitance) generators: prr = 1 mhz, 50% duty cycle, t r <6 ns, z o = 50 90% 90% 1.5 v 1.5 v 3 v0 v t plh t phl v oh v ol t r t f input b input a output y 10% 10% 1.5 v v id v o i o v a v b
9 SN65LBC175A-EP www.ti.com sllseu5 ? december 2016 product folder links: SN65LBC175A-EP submit documentation feedback copyright ? 2016, texas instruments incorporated parameter measurement information (continued) figure 10. test circuit and waveform ? transient overvoltage test figure 11. equivalent input and output schematic diagrams 16 v 16 v 100 k 18 k 4 k 4 k input a input v cc 16 v 16 v 100 k 18 k 4 k 4 input b input v cc 1 k 8 v 100 k v cc input enable input v cc 5 8 v 8 v y output output pulse generator, 15 s duration, 1% duty cycle 100 v test 0 v 15 s 1.5 ms v test
10 SN65LBC175A-EP sllseu5 ? december 2016 www.ti.com product folder links: SN65LBC175A-EP submit documentation feedback copyright ? 2016, texas instruments incorporated 8 detailed description 8.1 overview the SN65LBC175A-EP is a quadruple differential line receiver with tri-state outputs, designed for tia/eia-485 (rs-485), tia/eia-422 (rs-422), and iso 8482 (euro rs-485) applications. this device is optimized for balanced multipoint bus communication at data rates up to and exceeding 50 million bits per second. the transmission media may be twisted-pair cables, printed-circuit board traces, or backplanes. the ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. the receiver operates over a wide range of positive and negative common-mode input voltages, and features esd protection to 6 kv, making it suitable for high-speed multipoint data transmission applications in harsh environments. these devices are designed using linbicmos ? , facilitating low-power consumption and robustness. two en inputs provide pair-wise enable control, or these can be tied together externally to enable all four drivers with the same signal. 8.2 functional block diagram 8.3 feature description the device can be configured using the enable inputs to select receiver output. the high voltage or logic 1 on the en pin allows the device to operate on an active-high, and having a low voltage or logic 0 on the en enables active-low operation. these are simple ways to configure the logic to match the receiving or transmitting controller or microprocessor. 8.4 device functional modes the receivers implemented in the rs-485 device can be configured using the en logic pins set to enabled or disabled. this allows users to ignore or filter out transmissions as desired. 1a1b 1y 2a2b 2y 3a3b 3y 4a4b 4y 1,2en 3,4en copyright ? 2016, texas instruments incorporated
11 SN65LBC175A-EP www.ti.com sllseu5 ? december 2016 product folder links: SN65LBC175A-EP submit documentation feedback copyright ? 2016, texas instruments incorporated (1) h = high level, l = low level, x = irrelevant, z = high impedance (off), ? = indeterminate table 1. function table (1) differential inputs enable output a - b (v id ) en y v id ? 0.2 v h l ? 0.2 v < v id < ? 0.01 v h ? ? 0.01 v v id h h x l z x open z short circuit h h open circuit h h
12 SN65LBC175A-EP sllseu5 ? december 2016 www.ti.com product folder links: SN65LBC175A-EP submit documentation feedback copyright ? 2016, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information extending spi operation over rs-485 link. 9.2 typical application the following block diagram shows an mcu host connected via rs-485 to a spi slave device. this device can be an adc, dac, mcu, or other spi slave peripheral. figure 12. dsp-to-dsp link via serial peripheral interface 9.2.1 design requirements this application can be implemented using standard spi protocol on dsp or mcu devices. the interface is independent of the specific frame or data requirements of the host or slave device. an additional but not required handshake bit is provided that can be used for customer purposes. 9.2.2 detailed design procedure the interface design requirements are fairly straight forward in this single source/destination scenario. trace lengths and cable lengths need to be matched to maximize spi timing. if there is a benefit to put the interface to sleep, gpios can be used to control the enable signals of the transmitter and receiver. if gpios are not available, or constant uptime needed, both the enables on transmit and receive can be hard tied enabled. mcu or dsp spi master spisimo sn65lbc174a-ep SN65LBC175A-EP peripherial spi slave spi mosi spi cs spi clk gpio optional handshaking gpio or tie enabled spiclk spisomi spi miso gpio or tie enabled gpio optional handshaking copyright ? 2016, texas instruments incorporated gpio or tie enabled 2 spi cs gpio or tie enabled 2
13 SN65LBC175A-EP www.ti.com sllseu5 ? december 2016 product folder links: SN65LBC175A-EP submit documentation feedback copyright ? 2016, texas instruments incorporated typical application (continued) the link shown can operate at up to 50 mbps, well within the capability of most spi links. 9.2.3 application curve figure 13. receiver inputs and outputs, 50-mbps signaling rate a, b 500 mv 5 v ?500 mv 0 v 20 ns y
14 SN65LBC175A-EP sllseu5 ? december 2016 www.ti.com product folder links: SN65LBC175A-EP submit documentation feedback copyright ? 2016, texas instruments incorporated 10 power supply recommendations place 0.1- f bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high- impedance power supplies. 11 layout 11.1 layout guidelines for best operational performance of the device, use good pcb layout practices including: ? noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the operational amplifier. bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. ? connect low-esr, 0.1- f ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. ? place termination resistor as close as possible to the input pins (if end point node). ? keep trace lengths from input pins to bus as short as possible to reduce stub lengths and reflections on any nodes that are not end points of bus. ? to reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. if it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace. 11.2 layout example figure 14. layout with pcb recommendations v cc 0.1 f v dd 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 reduce logic signal trace when possible 4b 4a 4y 3,4en 3y 3a 3b 2b 2a 2y 1,2en 1y 1a 1b termination resistor
15 SN65LBC175A-EP www.ti.com sllseu5 ? december 2016 product folder links: SN65LBC175A-EP submit documentation feedback copyright ? 2016, texas instruments incorporated 12 device and documentation support 12.1 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 12.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.3 trademarks e2e is a trademark of texas instruments. linbicmos is a registered trademark of texas instruments. all other trademarks are the property of their respective owners. 12.4 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions.
16 SN65LBC175A-EP sllseu5 ? december 2016 www.ti.com product folder links: SN65LBC175A-EP submit documentation feedback copyright ? 2016, texas instruments incorporated 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 21-dec-2016 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples sn65lbc175amdrep preview soic d 16 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 lbc175aep (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
package option addendum www.ti.com 21-dec-2016 addendum-page 2 other qualified versions of SN65LBC175A-EP : ? catalog: sn65lbc175a note: qualified version definitions: ? catalog - ti's standard catalog product

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